Distinguish the two levels
SpinalHDL uses Scala to describe hardware and generate HDL. Successful Scala compilation is only one stage: the design still needs elaboration and checks on the resulting circuit. Start with the official template and preserve a working configuration. Ask AI to distinguish generation-time calculations from logic that must exist in hardware, especially around loops and conditional construction.
Constrain the parameters
For a register or FIFO generator, record valid widths and depths, reset behavior and transfer protocol. Decide how invalid configurations should fail. Ask AI for a matrix covering minimum, ordinary and boundary values. Do not promise arbitrary depth if the architecture actually requires powers of two; make that restriction visible in the contract and its checks.
Generate reproducibly
The official template example uses the entry point projectname.MyTopLevelVerilog. Run the command below from the prepared template root; replace the class name for another project. Record dependency versions, parameters and output location. Investigate elaboration diagnostics, then inspect generated ports, widths and reset blocks before connecting the RTL to the rest of the system.
sbt "runMain projectname.MyTopLevelVerilog"Check each configuration
For the selected matrix, run generation, self-checking simulation and synthesis with a suitable tool. Compare protocol behavior, latency and resources, rather than only error counts. Ask AI for additional edge cases using the actual reports. Store each result with its configuration: a verified 8-bit variant does not automatically validate a 32-bit variant.
Checks before accepting the result
The unit of generator verification is a configuration together with its RTL and reports.